The present invention relates to non-volatile memory cells integrated on a chip with logic transistors and/or high voltage transistors.
One of the most serious limiting factors in scaling the tunnel oxide in floating gate non-volatile memory cells is stress-induced leakage current (SILC). For oxides thinner than 8 nm the ability to store charge on the floating gate of a memory cell becomes questionable. It has been demonstrated that the characteristics of the tunnel oxide change as a result of passing charge through the oxide. Program/erase cycles weaken the ability of the oxide to isolate the floating gate from a substrate. Some believe that non-volatile memory oxide scaling much below 8 nm is difficult and perhaps impossible unless the 10-year charge retention requirement for non-volatile memory cells is relaxed. Some have even suggested that xe2x80x9cnon-volatilexe2x80x9d memories may have to be xe2x80x9crefreshedxe2x80x9d periodically like DRAMs, but not nearly as frequently, in order not to lose the data stored. This may be a viable solution for some applications, however, the concept of xe2x80x9cnon-volatilexe2x80x9d changes to xe2x80x9cnot-so-much-volatilexe2x80x9d. Besides, xe2x80x9crefreshingxe2x80x9d may lead to failure. One application that could have problems with this approach is the xe2x80x9csmart-cardxe2x80x9d, which could lose vital information if refreshing does not occur, and these cards are often not connected to a power supply for long periods of time.
If the tunnel oxide is limited to 8 nm, or a higher value, it will be difficult to make a cost-effective, non-volatile memory module embedded in an advanced CMOS logic process. In such a process, floating gate non-volatile memory cells are manufactured on the same substrate as logic CMOS transistors. The gate oxide thicknesses of the CMOS logic transistors are typically in the order of 5 nm or less.
Assuming that Folwer-Nordhein tunneling is used for at least one of the programming or erasing procedures, the thickness of the tunnel oxide in the memory cell, in combination with the coupling ratio of the control gate to the floating gate, determines the voltage necessary for the efficient transfer of charge to and/or from the floating gate. In particular, a tunnel oxide in the range from 8 to 9 nm will usually require a voltage of such high level that it is necessary to include high voltage transistors on the substrate for controlling this high voltage. The gate oxide of these high voltage transistors must be much thicker than the tunnel oxide of the memory cells: typically, 15 to 25 nm is used.
Moreover, there is an insulating layer between the control gate and the floating gate of the memory cell, which is typically made of oxide-nitride-oxide (ONO).
Therefore, in a process in which floating gate memory cells, logic transistors and high voltage transistors must be made on the same substrate there are typically at least the following four oxide/insulating layers:
the tunnel oxide of the memory cell;
the gate oxide of the high voltage transistor;
the gate oxide of the logic transistor; and
the insulating layer between the control gate and the floating gate of the memory cell.
Until now these oxide-insulating layers were provided in different thicknesses, thereby adding to the costs of the process and introducing reliability risks.
H. Watanabe, e.a., xe2x80x9cScaling of Tunnel Oxide Thickness for Flash EEPROMs Realizing Stress-Induced Leakage current Reductionxe2x80x9d, 1994 Symposium on VLSI Technology Digest of Technical Papers, 1994, pp. 47-48, discloses a method for reducing stress-induced leakage current (SILC) in floating gate non-volatile memory cells. One of the measures taken is to lower the floating gate impurity concentration. As a result, the SILC level is reduced to such a level that the thickness of the tunnel oxide below the floating gate can be reduced to about 6 nm. In order to prevent an increase of the programming voltage to due to the lowered impurity concentration, it is proposed to apply an impurity concentration of 5 to 7xc3x971019 cmxe2x88x923.
T. Kubota, e.a., xe2x80x9cThe Effect of the Floating Gate/Tunnel SiO2 Interface on FLASH Memory Data Retention Reliabilityxe2x80x9d, NEC Research and Development, Vol. 38, 1997, No. 4, pp. 412-418, state that the data retention time of a floating gate memory cell will be enhanced by lowering the impurity concentration since this will lower the SILC level.
By using the proposals made by Watanabe, e.a., and Kubota, e.a., it would be possible to scale the thickness of the tunnel oxide similarly as the process scales for the next generation. It is envisaged that gate oxides having thicknesses in the order of 2 to 5 nm will be used.
By making cells with a thin, very lightly doped polysilicon floating gate, it is possible to make such thin tunnel oxides and still have an acceptable level of SILC.
The object of the present invention is to provide a simplified method of manufacturing on a single substrate at least one memory cell and at least one logic transistor.
In order to achieve this object, the present invention claims a method of manufacturing on a single substrate at least one memory cell and at least one logic transistor;
the at least one memory cell comprising a floating gate, a tunnel oxide layer between the floating gate and the substrate, a control gate, and a control oxide layer between the control gate and the floating gate;
the at least one logic transistor comprising a logic transistor gate and a logic transistor gate oxide between the logic transistor gate and the substrate, characterized in that the tunnel oxide layer of the memory cell and the logic transistor gate oxide are made in a same step and have a same or substantially same predetermined first thickness.
Since it is possible to control the SILC level by choosing a proper impurity concentration of the non-volatile memory floating gate, the tunnel oxide layer thickness of the memory cell can be designed such that it is equal to the thickness of the logic transistor gate oxide. Thus, they can be made in the same step of the process, which reduces costs and enhances reliability.
A similar approach can be used to simplify the process of integrating floating gate memory cells and the high voltage transistors needed for the programming and deprogramming of the memory cells on the same substrate. Therefore, the invention also relates to a method of manufacturing on a single substrate at least one memory cell and at least one high voltage transistor;
the at least one memory cell comprising a floating gate, a tunnel oxide layer between the floating gate and the substrate, a control gate, and a control oxide layer between the control gate and the floating gate;
the at least one high voltage transistor comprising a high voltage transistor gate and a high voltage transistor gate oxide between the high voltage transistor gate and the substrate,
characterized in that the high voltage transistor gate oxide comprises a first gate oxide layer on top of the substrate and a second gate oxide layer on top of the first gate oxide layer,
in that the first gate oxide layer and the tunnel oxide layer of the memory cell are made in a same first step and have a same or substantially same predetermined first thickness,
and in that the second gate oxide layer and the control oxide layer of the memory cell are made in a same second step and have a same or substantially same predetermined second thickness.
By splitting up the gate oxide of the high voltage transistor into a first gate oxide layer and a second gate oxide layer, with the first gate oxide layer thickness being made in the same manufacturing step as the tunnel oxide of the memory cell and the second gate oxide layer being made in the same manufacturing step as the insulating layer between the control gate and the floating gate of the memory cell, a more cost-effective and more reliable process is obtained. Then, both the thicknesses of the tunnel oxide, the insulating layer between the control gate and the floating gate in the memory cell and the gate oxide of the high voltage transistor can be designed in accordance with any requirement because the doping concentration of the floating gate of the memory cells can be selected so as to be low enough to provide the required freedom of design.
These processes can also be integrated in order to have memory cells, logic transistors and high voltage transistors integrated on one single substrate in accordance with the invention.
Then, instead of four different oxide/insulating layers there are only two: a first oxide layer directly on the substrate, that is used as a tunnel oxide in the memory cell, as a gate oxide in the logic transistor, and as the first gate oxide layer in the high voltage transistor, and a second oxide layer which is used as an insulating layer between the control gate and the floating gate of the memory cell and as a second gate oxide layer in the high voltage transistor. It is evident that such an integrated process is cheaper than the process in accordance with the prior art because fewer masks are needed and fewer process steps are required.
The thickness of the tunnel oxide, the first gate oxide layer and the gate oxide layer of the logic transistor is preferably in the range between 2 and 10 nm, even more preferably between 4 and 8 nm.
The doping concentration of the floating gate is preferably less than 1xc3x971020 per cm3, preferably less than 4xc3x971019 cmxe2x88x923.
A further advantage can be obtained if the logic gate transistor comprises a first gate layer on top of the logic transistor gate oxide and a second gate layer on top of the first gate layer. The first gate layer and the floating gate are preferably made simultaneously and have the same or substantially same predetermined third thickness and the same or substantially same predetermined doping concentration.
The second gate layer of the logic transistor is preferably made in the same manufacturing step as, if applicable, the gate of the high voltage transistor.
The present invention does not only relate to a method but also to a semiconductor device comprising on a single substrate at least one memory cell and at least one logic transistor;
the at least one memory cell comprising a floating gate, a tunnel oxide layer between the floating gate and the substrate, a control gate, and a control oxide layer between the control gate and the floating gate;
the at least one logic transistor comprising a logic transistor gate and a logic transistor gate oxide between the logic transistor gate and the substrate, characterized in that the tunnel oxide layer of the memory cell and the logic transistor gate oxide have a same or substantially same predetermined first thickness.
In a further embodiment the present invention also relates to a semiconductor device comprising on a single substrate at least one memory cell and at least one high voltage transistor;
the at least one memory cell comprising a floating gate, a tunnel oxide layer between the floating gate and the substrate, a control gate, and an a control oxide layer between the control gate and the floating gate;
the at least one high voltage transistor comprising a high voltage transistor gate and a high voltage transistor gate oxide between the high voltage transistor gate and the substrate,
characterized in that the high voltage transistor gate oxide comprises a first gate oxide layer on top of the substrate and a second gate oxide layer on top of the first gate oxide layer,
in that the first gate oxide layer and the tunnel oxide layer of the memory cell have a same or substantially same predetermined first thickness, and in that the second gate oxide layer and the control oxide layer of the memory cell have a same or substantially same predetermined second thickness.